Priority is claimed to Japanese Application No. 2005-063580 filed on Mar. 8, 2005, which is hereby incorporated by reference in its entirety.
1. Technical Field
The present invention relates to a semiconductor and a method of manufacturing a semiconductor, more particularly to a method for forming a SOI structure and bulk structure on the same substrate.
2. Related Field
The utility of a field effect transistor formed on a SOI substrate is well known because of the ease of isolating elements, avoiding latch up, and small source and drain contact capacitance. In theory, a perfect depletion SOI transistor is capable of fast driven operation with low power consumption and is easily driven by low voltage, enhancing active research for driving SOI transistors with the prefect depletion mode. Here, as a SOI substrate, a substrate of separation by implanted oxygen (SIMOX) and an attached substrate are used. JA2002-299591 and JA2000-124092 are examples of related arts.
Here, when a complementary metal oxide semiconductor (CMOS) is formed by using a SOI transistor, a P channel transistor is placed adjacent to an N channel transistor on the same second dimension plane and formed on the semiconductor having a {100} crystal face.
On the other hand, it is difficult to form a field effect transistor having a high current drive power and a high break down voltage on a SOI substrate of which thickness is constrained. Such a transistor is preferably formed on a bulk substrate. Further, JA 10-261799 discloses a method of forming a highly uniform and highly crystallized silicon thin film on a large area of an insulating film, wherein a polysilicon film has square shaped mono crystalline grains arranged in a matrix. The polysilicon film is formed on a insulating film by irradiating UV pulse beams to an amorphous or poly crystalline silicon film formed on a insulating film and the surface of the polycrystalline film is planarized with chemical and mechanical polishing (CMP.)
However, it is necessary to ion implant highly concentrated oxygen into a silicon wafer for forming a SIMOX substrate. Further, in order to manufacture an attached substrate, it is necessary to polish the surface of a silicon wafer after attaching two silicon wafers. Hence, there exists a problem of increasing manufacturing cost on a SOI transistor compared to a field effect transistor formed with a bulk semiconductor.
Further, there is the additional problem of difficulty in stabilizing characteristics of a field effect transistor when an SOI layer is thinned for manufacturing a perfect depletion SOI transistor because of large variation of the thickness of a SOI layer during ion implantation and polishing. Further, there is the additional problem of difficulty in high integration because of enlarging a necessary area for forming a CMOS circuit when a P channel field effect transistor and a N channel field effect transistor are placed on the same two dimensional plane. Further, there is the problem of enlarging wiring, which is necessary for connecting a P channel field effect transistor with a N channel field effect transistor, yielding transmission delay. When a CMOS circuit is formed on the semiconductor having the {100} crystal face, it is necessary that the channel width of a P channel field effect transistor is two or three times wider than that of a N channel field effect transistor due to the difference of mobility between electrons and holes. Thus, there is difficulty in high integration of elements since the layout balance between a P channel field effect transistor and a N channel field effect transistor is altered because of the above reason.
Further, in the silicon thin film formed on an insulating film by the method disclosed in JA 10-261799, micro defects such as grain boundary and micro twin exist. Hence, there is a problem of inferiority in characteristics of a transistor formed with a silicon thin film compared to a transistor made with a perfect crystalline silicon thin film. Further, when multi layered field effect transistors are deposited, a field effect transistor exists in the bottom. Hence, this structure deteriorates the planarization of a lower insulating film on which the upper silicon thin film is formed. Further, there is a problem of inferiority of crystallization in the upper silicon thin film comparing to the lower silicon thin film since thermal and other conditions for forming the upper silicon thin film are constrained.
Hence, in the conventional semiconductor device, a SOI structured device, which is made of defect free mono crystal, can not be installed on bulk silicon. Further, a device having three dimensional structure in which perfect crystalline silicon thin films having various thickness are deposited can not be realized.